The present invention relates, in general, to semiconductor structures, and more particularly to a silicon on insulator structure having both complementary bipolar and CMOS devices.
One of the fundamental parameters of integrated circuit manufacture is the electrical isolation which is provided between the different devices which comprise the integrated circuit. Typically a reversed biased semiconductor junction has been utilized for this purpose. However, it has long been recognized that isolation using a high quality insulating material such as silicon dioxide, greatly enhances the performance of integrated circuits in just about every way. For example, integrated circuits intended for military applications which must operate in the presence of ionizing radiation typically use some form of silicon on insulator (SOI). Numerous methods of fabricating such SOI integrated circuits have been used in the past, including methods such as separation by oxygen implantation or SIMOX. More recently bonded wafer methods have produced a silicon film having a low defect density, but with poor control of thickness of the silicon film above the oxide.
The prior art includes numerous methods for fabricating transistors in bulk silicon which utilize a vertically oriented structure. While vertical structures are suitable to bulk silicon, they are difficult to fabricate in a very thin film. In addition such structures do not take advantage of the low parasitic potential of thin film SOI. A method for fabricating a horizontal bipolar transistor on an SOI substrate was described in the paper "A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI", by N. Higaki et al., 1991 VLSI symposium technical digest, pages 53 to 54, which is incorporated herein by reference. This method allows for fabrication of bipolar transistors on an SOI substrate, however the method of fabrication produces a long thin base area with electrical contact provided only at either end of the base structure. The resultant high base resistance degrades the device performance, reducing achievable bandwidth, noise, and switching speed. Another method for fabricating a horizontal bipolar transistor on an SOI substrate was presented in the paper "A NOVEL HIGH-PERFORMANCE LATERAL BIPOLAR ON SOI" by G. G. Shahidi et al., 1991 IEDM, pp 26.1.1-26-1.4. This method addresses the base resistance problem, but requires added process complexity to form a polycrystalline silicon spacer on only one side of the base opening.
There is a need for a method for fabricating both complementary bipolar and CMOS (BiCMOS) transistors using an SOI method which allows a much simplified lateral isolation between devices. The method should utilize a horizontal structure so as to minimize parasitic effects, especially base resistance. Ideally, the method should use the minimum number of mask steps, fabricate self-aligned transistors and should integrate fabrication of both complementary bipolar and CMOS transistors into a single manufacturing flow requiring a minimum of extra steps devoted solely to one transistor type.